IO (input/output) links for electronic device in communication may be implemented in various forms, including parallel and serial link implementations. Because of cost advantages offered by differential high-speed IO (HSIO) serial link technology, the serial HSIO became an attractive alternative over the conventional parallel IO. Commonly addressed disadvantages of parallel IO may include high pin count, routing resource, and skew among parallel data bits.
An HSIO serial link provides a high-bandwidth communication channel that may match or exceed data rate of parallel IO. A parallel data may be serialized before transmission, and received serialized data may be de-serialized into parallel data at the receiver. The HSIO serial links may reduce pin count and simplify layout issues by eliminating trace match and congestion. Because data is transmitted serially, there is no need to maintain phase relationships among individual data bits.
A serial link may provide for differential signaling. Differential signaling may be used to immunity against certain common noise. The differential interconnection may be utilized to efficiently remove the common noise added during transmission. In operation, the HSIO interconnections may carry the clock signals and the transmitted data, with the clock signals embedded into the data or provided separately.
An HSIO serial link commonly employs a differential signaling scheme. Differential signaling uses a pair of wires: one of the wires carries a signal (which may be referred to as Vp(t)), while the other wire carries the inverse of the signal (Vn(t)). The wires that carry Vp(t) and Vn(t) are referred to as the positive and negative interconnection wires respectively. A receiver may recover data based on the difference between the signals being propagated on the complementary interconnection wires. The difference between the signals, which may be denoted as Vdiff(t), may be defined as Vdiff(t)=Vp(t)−Vn(t). Noise that is added to both Vp(t) and Vn(t) during transmission may be subtracted away, and thus be removed from the Vdiff(t).
The sign of Vdiff(t) may be interpreted as an intended logic value. That is, ideally, the positive or the negative value of Vdiff(t) may be interpreted as logical ‘1’ or ‘0’ respectively. If, for example, Vp(t)=250 mV and Vn(t)=−250 mV, then Vdiff(t)=500 mV>0 may be interpreted as logical ‘1’. Similarly, Vdiff(t)=−500 mV<0 may be interpreted as logical ‘0’ if Vp(t)=−250 mV and Vn(t)=250 mV. In practice, the minimum value of Vdiff(t) for logical ‘1’ and ‘0’ may be smaller than Vp(t) and Vn(t) respectively. This thus may allow the serial link to be functional and not necessarily to be failed even if one of differential IO lines is defective. However, this may create a potential test problem when defects may be masked during a test, but may cause failure in system application. Thus, detection and proper diagnosis of such defects may be challenging in an HSIO interconnection test.